( GPIOTest)
( 10th August 2015)

HEX 200 20200000 DECIMAL 13 SPI_reg BINARY
CONSTANT GPIOsel_fn
HEX
GPIOsel_fn 1C + CONSTANT OutSet0
GPIOsel_fn 28 + CONSTANT OutClr0

DECIMAL
0 VARIABLE FNsel_addr     ( address of Function select register for pin no)
0 VARIABLE 3bits_addr     ( offset address for selection code in above register)
0 VARIABLE OPSetReg       ( addr of Pin Set regs 0 to 1 - for pin no)
0 VARIABLE OPClrReg       ( addr of Pin Clear "" ) 
0 VARIABLE 1bit_addr      ( offset into Set/Clear registers)

HEX
( swap 0s and 1s)
: NOT  ( n...n)  FFFFFFFF XOR ;
DECIMAL

( 3 bits cleared using AND NOT and then 001 inserted using OR)
: pin_out   ( pin no...)
   DUP
   7  SWAP 3 *  <<   ( 7=111)
   NOT
   GPIOsel_fn rd_SVCmode                 
   AND
   ( 001 for output:)
   1  ROT  3 *  << OR
   GPIOsel_fn wr_SVCmode ;
DECIMAL

( pins high/low words:)

: pin_high ( pin no....)  1 SWAP << OutSet0 wr_SVCmode ;  ( 1=high)
: pin_low  ( pin no....)  1 SWAP << OutClr0 wr_SVCmode ;  ( 1=low)

: Pin_toggle   ( n...)
  DUP pin_out
  5 0 DO DUP pin_high  KEY DROP 
         DUP pin_low   KEY DROP 
      LOOP DROP ;

( **** General forms of the above, using >=1 registers: ****)
( show contents of registers via SVC mode)
: see_reg ( addr...n)  rd_SVCmode BINARY U. DECIMAL ;
: ?GPIOsel_fn  GPIOsel_fn see_reg ;
: ?OutSet0     OutSet0  see_reg ;
: ?OutClr0     OutClr0  see_reg ;

( show address, not contents)
: ?FNsel_addr  FNsel_addr @ CR BINARY U. SPACE GPIOsel_fn U. DECIMAL ;
: ?3bits_addr  3bits_addr @ CR BINARY U. DECIMAL ;
: ?OPSetReg    OPSetReg   @ CR BINARY U. SPACE OutSet0 U. DECIMAL ;
: ?OPClrReg    OPClrReg   @ CR BINARY U. SPACE OutClr0 U. DECIMAL ;
: ?1bit_addr   1bit_addr  @ CR BINARY U. DECIMAL ;
: showregs ?FNsel_addr ?3bits_addr ?OPSetReg ?OPClrReg ?1bit_addr ; 
           
: GPIOFNsetup ( pin no...)
  ( set Function select register stuff:)
  10 /MOD                   ( remainder,ratio...)
  4* GPIOsel_fn +           ( remainder,addr of sel register...)
  FNsel_addr !              ( remainder...)
  3 * ( <<) 3bits_addr ! ;  ( ...)  ( points to l.sig bit of 3)

  ( set write/clear register stuff:)
: SetClrsetup ( pin no...)
  32 /MOD                     ( remainder,ratio...)
  4* DUP OutSet0 + OPSetReg !
         OutClr0 + OPClrReg !
  1bit_addr ! ;

( 3 bits cleared using AND NOT and then 001 inserted using OR)
: gpin_out   ( pin no...)  ( set a Function Reg to output for this pin no)
   DUP GPIOFNsetup
   7 SWAP 3 * <<           ( 7=111)
   NOT
   FNsel_addr @ rd_SVCmode                 
   AND
   ( 001 for output:)
   1  3bits_addr @ ( 3 *)  << OR
   FNsel_addr @  wr_SVCmode ;

: gpin_high ( pin_no...)
  SetClrsetup  OPSetReg @  1bit_addr @  ( SET reg address,effective pin no...)
  1 SWAP << SWAP  wr_SVCmode ;

: gpin_low   ( pin no...)
  SetClrsetup   OPClrReg @  1bit_addr @     ( CLR reg address,effective pin no...)
  1 SWAP << SWAP  wr_SVCmode ;









